Digital Circuit Report of Leading Experiment I
B82503007 Ing-Jei Huang
B82503081 Lan Chang
B82503131 Murphy Chen
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System Overview
by b82503131
There are three lights (red, yellow, and green) in the traffic sign on the road. When the power turns off, the traffic lights do not work at all. When the power turns on, the whole system begins to work.
There is one switch to determine whether the system is in normal state or in special state. When the switch turns off, the whole system will enter the special state, and the yellow light is turned on and turned off repeatedly. When the switch turns on, the whole system will behave normally, the sequence of the traffic sign is green, yellow, and red, and they will be turn on in turn repeatedly until the power is off or the switch is turned off.
The intervals of the red and green lights are adjustable. The ranges which are set by DIP switches are within 99 seconds. The yellow one is always 8 seconds. The interval of the green light is adjusted by BCD numbers, but the interval of the red light is adjusted by binary numbers. The user can adjust the intervals at any time, and the whole system will still work. One exception is that when the user adjust the interval of the light shorter than the passed time since the same light has been turned on, and has not turned off to switch to next light.
Whenever a light has been turned on, a counter of that light will first clear to zero and then start to count, and the value of the counter will show on the LEDs of that light. When the counter has counted to the specified interval of that light, it will stop counting, and the next light will be turned on, completing the cycle.
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Introduction & Design of Each Subsystem
A. Clock Unit -- By b82503131
The clock is used to generate the clock of the synchronous system. There are two clocks in the system: one is a 4Hz clock for the Control Unit, the other is a 1Hz clock for the Counter Unit. The reason to provide the Control Unit with faster clock rate than 1Hz is to minimize the time delay the Control Unit may induce when switching from one state to another. If we provide the Control Unit with only 1Hz clock, the time delay between a state transition can be as high as 1 second, which is not acceptable. So we must provide a faster clock for the Control Unit.
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The 4-Hz clock is generated from 74LS123, as Fig xxx shows. Two one-shots, or two sections of a dual one-shot such as the 74LS123, can be coupled together to produce an oscillator. When a pulse on one of the one-shots expires, the resulting negative-going edge triggers the other one-shot. If this is allowed to continue indefinitely, the circuit functions as an oscillator or clock generator.
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The 1-Hz clock is generated from the division of 4-Hz clock. The first I design the circuit I use the algorithm as follows: To construct an n stage synchronous counter, do the following:
1. AND together the Q outputs of stages 0, 1, ..., n-1.
2. Connect the output of the AND gate to the input of an XOR gate. The other input to the XOR gate must be connected to Qn.
3. The output of the XOR gate must be connected to Dn.
And the resulting circuit will use two DFFs and one XOR gate, as shown below:
The second time, after discussing with classmates from other groups, I use another circuit, which uses less gates, and the circuit works just as good as previous one. So, finally we decide to use the second circuit, as shown in the beginning of this page.
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B. Input Unit -- By b82503131
The input unit includes a toggle switch and two DIP switches. The toggle switch is used to determine whether the system is in normal state or in special state as explained before. The switch is connected to a debouncing circuit to avoid the undetermined states between on and off. The debouncing circuit works as follows: A noisy switch can be debounced by connecting its outputs to the direct SET and CLEAR of a 74x74 FF as shown below. When the switch is in the UP position, the LOW input at point A keeps the FF in the SET position. The bounces which occur when the switch leaves the upper position do not affect the FF. When the switch starts to engage the lower contact, the first bounce clears the FF. The other bounces merely serve as additional CLEAR pulses and have no further effect on the FF. Therefore, the FF produces a single output change, as required, when the switch is thrown from UP to DOWN. The situation is similar when the switch is thrown to the UP position. The FF does not set until the first negative bounce occurs when the blade starts to engage the upper contact. The following bounces merely serve as additional SET pulses. The FF is a successful debouncing circuit because only a single transition occurs for each throw of the switch.
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The DIP switches do not suffer from the problem of switch bouncing, because the clock of the system is 4-Hz and the bouncing of the switch is far less than the period of the clock. So it has no side-effects on the whole system operation. The DIP switches are configured in such a way that when one pin of the switch is moved down, it really mean zero, and when it is moved up, it really means one. To make this possible, the zero-side of the switch is connected with a resistor and to the ground, and the one-side of the switch is connected to the Vcc, and take the zero-side of the switch as outputs. So, when one pin of the switch is moved down, the one-side and the zero-side will become unconnected, and the output is connected with a resistor to the ground, we get a zero. When one pin of the switch is move up, the one-side and the zero-side will become connected, and the Vcc will have its voltage drop on the resistor, so the output will become one. But when we really test this circuit, we found that when one pin of the switch is moved down, the output will be about 1.2V, this shows that there still has a resistor effect when one pin of the switch is moved down, so we adjust the value of the resistors at the zero-side of the switch so that when one pin of the switch is moved down, the output voltage will be close to 0V as good as possible.
C.ROM -- by b82503131
We use a ROM whose type is 2716 to act as a decoder to decode binary numbers to BCD numbers. The concept of a ROM is simple, the user supplies an address and the ROM provides the data output of the word pre-written at that address. We first write BCD numbers at corresponding binary address into the ROM, so that when we provide the ROM with binary numbers as addresses, the ROM will provide corresponding BCD numbers as outputs. The address line of the ROM is larger than 7, but we only need 7 bit inputs, so we can connect the other unused MSB of address bits to ground.
D. Interval Display Unit – b82503007
The function of this unit is to display the current value of interval counters. In this
unit, we will receive 6-bit signals from the red counter,4-bit signals from the yellow counter, and 8-bit signals from the green counter. Here we need five 7-segment displays, two for both green and red counters and one for yellow counter. This is due
to the capacity of these counters. The green counter's count ranges from 00 to 99, the red counter's ranges from 0x00 to 0x63. So both of them need two 7-segment displays. As to the yellow counter, because of its capacity of constant 8 seconds, we just need one 7-segment display.
Between the BCD inputs from green counter and the 7-segment display, we
need decoders which convert the BCD inputs to 7 segments outputs accepted by the display. According to the specification, the red and yellow counters use 74LS47, and
the green counter use 74LS48. As to the difference between 7447 and 7448, we will discuss in the later "selected topic" part. Because of this specification, two kinds of 7-segment displays muse be used. CA 7-segment display is used for red and yellow counters and CC 7-segment display is for green counter.
In this unit, the BCD inputs of 74LS48 is fed by the outputs QA, QB, QC, QD of
74LS160, the 4-bit BCD counter. Then the output of 74LS48 will be the appropriate
codes needed for the CC 7-segment display. Here we need two 74LS48s for the 8- bit signals from the green counter. To cascade the two 74LS48s, we connect the RBI pin of the higher-bit 7448 to Vcc, and its RBO pin is connected to the RBI pin of the lower-bit 7448. In this way ,when the higher bit of green counter is zero, it will still show a zero, not becoming blanking.
The case for yellow counter is almost the same with green ones except that yellow counter has only one digit, so no cascading is needed. As to the red counter, because it is a binary counter, whose output is not suitable for 74LS47, we need one decoder between 74LS162 and 74LS47, which converts the binary codes to the BCD codes.We use a ROM to implement it. Then just like the green ones, 7447 is fed with BCD codes and its seven outputs is connected to the CA 7-segment displays.
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D. Traffic Counter Unit – b82503007
This block 's function is to count the intervals and compare the values. It will do the counting action, and compare with the values set by the user. Until the counters' value and user's setting is matched, it will disable the current acting counter, send a signal to the control unit , and then the next counter will be activated. In this unit, we use three kinds of counters. The first one is 74LS161, which is a 4-bit binary counter and used for the red light. The second one is 74LS160, which is a 4-bit BCD counter and used for the green light. The last one is 74LS193, which is a 4-bit up-down counter and used for the yellow light. For the green counter, comparison is done with one 74LS86 which contains eight 2-input XORs. For the red counter, we use one 74LS85 which is a 4-bit comparator and 3 2-input XORs. As to the yellow counter, owing to the assigned 8 or 9 seconds , we don't need any comparators.
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As mentioned above, we use 74LS160 to implement the green counter. Because the counter's count ranges from 00 to 99, we have to cascade two74LS160s by connecting the RCO pin of the lower-bit 74160 to the ENT pin ofhigher-bit 74160. Concerning the communication with the control unit, our design is when the counter's value is matched with the user's input, the output of comparison will send a LOW signal to disable this counter. In the meanwhile, this LOW signal will also be sent to the control unit which will be informed that the green light's period is over, and ought to enable the yellow light. Because the green counter is disabled, it's output will keep the last count. Though it's not counting, it will still show the last count value on the display. The green counter will be activated again when the red light's period is over. At this time, the control unit will send a LOW pulse to the CLR pin which is active-low. Then the counter will be cleared causing the output of comparison to go HIGH and enable the counter again.
The design of red counter is almost the same with the green's except that we use
74LS161 instead of 74LS160, and some changes in the comparison circuit. As to the
yellow counter, due to its assigned value of 8 seconds. We can find that when it counts to eight, QD will transmit from LOW to HIGH which we can use to indicate the completion of its counting. So we connect the complement of QD to LOAD which is active-low. When QD goes HIGH, a LOW will be fed to LOAD to load the preset 1000 to its QA, QB, QC, QD, then the yellow counter will stop counting and keep this value until the control unit send a HIGH to its CLR pin, which starts the cycle again.
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E. Control Unit –by b82503081
The control unit will do the following tasks:
1. Receive the signal from the Counter Unit when one interval is end.
2. Send signals to the Counter Unit when the light changes.
3. Control the Traffic Light.(ON or OFF)
The waveform of the subsystem is as the waveform plot. The functions of the system is as follows:
(1) The first cycle is different from the following cycle because the Counter Unit uses the first cycle to initialize the Flip-Flops.
(2) When the switch is off, the function of the system is a flash yellow light, it is attained by the switch of STATE_INI and STATE_INI1 per clock cycle(4Hz).
(3) The first light on is green light.
(4) When a message of light changing is received from the Counter Unit, the light changes and an output to Counter Unit is sent, and then the Counter Unit start the next interval of light.
(5) The meaning of inputs and outputs are as follow:
a. CLK: the input of 4Hz clock, all function of the system uses this clock.
b. SW: the switch, when switch is on, the input voltage is high, and off is high.
c. IG: the input signal mainly about the green light, generally, when green light is on, the pin is high, and vice versa.
d. IY: the input signal mainly about the yellow light, generally, when yellow light is off, the pin is high, and vice versa.
e. IR: the input signal mainly about the red light, generally, when red light is on, the pin is high, and vice versa.
f. LG(Light of Green): Output to the green light, when it’s high, the green light is on.
g. LY(Light of Yellow): Output to the yellow light, when it’s high, the yellow light is on.
h. LR(Light of Red): Output to the red light, when it’s high, the red light is on.
i. OG(Output of Green): Output to the Counter Unit, mainly about the state of green light, generally, when the light changes to green, it sends a high pulse to the Counter Unit.
j. OY(Output of Yellow): Output to the Counter Unit, mainly about the state of yellow light, generally, when the light changes to yellow, it sends a low pulse to the Counter Unit.
k. OR(Output of Red): Output to the Counter Unit, mainly about the state of red light, generally, when the light changes to red, it sends a high pulse to the Counter Unit.
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F. Output Unit –by b82503081
1. Output the result of Control Unit so
drivers, riders, and walkers can see the
traffic light.
2. We use the buffer in 74LS126 to
be the
three states buffer.
3. The LEDs
is connected to the buffer,
when the input is high, the LEDs is on,
and vice versa.
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Discussions & Improvements
<B82503131>
1. Never leave unused pins open! In the design of clock unit, I encountered a big problem, ie. , the clock pulse was oscillated in a varying frequency, sometimes the result was right, sometimes not. I examined everywhere carefully in the circuit, but did not find anything wrong. I really could not believe it, how could it happen? And I tried to use another circuit and still another one, but in vain. After discussing with classmates from other groups, I guessed maybe the reason why my circuit could not work is just because I left unused pins open, assuming they would be high, but they didn’t act as I thought. After I connected those left-open pins to Vcc, everything was okay. With a relief, I think I have really learned a lesson.
2. The definition of the system operation is very important! We didn’t do very well in this aspect. After we’ve tested the input unit, clock unit, counter unit successfully, and been ready to put all the sub-systems together, there’s something wrong with the communication between the control unit and the counter unit. We take quite a lot of time debugging this kind of error several times. And they are usually induced by the ambiguous definition of the operation of the sub-systems. So, it is really important to make a clear definition of each sub-system in the beginning in order to avoid ambiguous relations with some sub-systems.
3. The function of our system is not much. Though, we are the fastest! Absolutely, we can incorporate more function as other groups. But there is a trade-off, between time and quality. We choose the former, because we think that we have learned so much in developing the system, and adding more function to the system leaves not much for us to learn. It’s just the question of time: the more time one uses, the more function he/she can add. But we do not need much time! J
4. We find that there is a binary-to-BCD IC (74185) can be used to replace the ROM(7416) we use in the system. However, in order to perform the same task as the ROM does, we need three 74185s, which cost nearly three times than a ROM. So, the determination of using a ROM instead of using three 74185s is a judicious choice.
<B82503007>
1. Interval Display Unit: This unit is not too hard but quite boring because of its wiring. There are 8 lines from the green counter, 4 lines from the yellow counter, and 7 lines from the red counter. And 5 7-segment displays, equally 35 lines, must be connected to 7447 or 7448. So lots of patience is necessary. Fortunately, it just costs time, but not too complicated circuit. Our failure in this block is the brightness of CC 7-segment is not enough. This is due to the low current output of 7448 which can't afford enough current for the normal brightness of LEDs. The right way is to use Vcc to supply the current needed by the LEDs. The output of 7447 or 7448 is just acting as switches. Then we can get the desired brightness of CC 7-segment displays. Another problem we met in this unit is the cascading of 7447 / 7448. First we cascade two 7447s in the way the textbook introduced which is called ripple blanking. But we think it’s not a good idea to blank out the leading zeros for general appearance. So we connect the RBI pin of higher-bit to Vcc, And the leading zero will appear on the display.
2. Traffic Counter Unit: In this unit, we met a lot of difficulties including some very trivial mistakes. One of them is that when we completed our wiring of the whole circuit, the green counter kept on counting and didn’t stop on its setting value. We debugged and debugged again. The control unit was no problem according to its simulation result. The connection between counters was also no problem. Finally, we found that the count value from the DIP switch gave us a 1V when it was zero. So the comparison of counter’s value and user’s setting value wouldn’t get the right result. This mistake came from different threshold voltages among various logics. This kind of logic’s zero may not be recognized by other logics. So interface between logics is very important and often ignored.
Our design in this unit is not optimal because we use extra ICs. First, in the comparison part , we use 7400, a NAND gate, to get a comparison result which will be sent to control unit. In fact, this logic can be implemented in the control unit, and this IC and be saved. It is of the same case to use an extra 7425. In the aspect of communication with the control unit, our design is to send a signal to both the control unit and the current counter’s enable pin. Then the control signal will send a signal to the next stage counter to enable it. The disable action is done by the counter itself. Actually, it is a better design to let the control unit to do this action, which will lead to a simpler design of control unit.
3. I have never used so many ICs on one breadboard. It’s really patience-consuming to do the wiring correctly and orderly. First I am not sure if my part will work correctly. So I don’t care the wiring very much. But finally the breadboard is full of wires which cross each other untidily. It’s really in a mess and not easy to debug. So at last, I still have to rearrange my wiring and make it as neat as possible. From this experiment , I really get many ideas about the digital circuit, and lots of frequently used ICs which I never have idea about before. Though it is really frustrating when we can’t find where the bug is, or make some trivial mistakes, such as no grounding, connecting GND to Vcc, and so on, the joy of seeing the circuit working properly is really great.
At last, I am really thankful to
my partners because we always do this experiment together. It will be quite
frustrating when you meet some problems, and nobody is beside you to help
you solve these problems. The feeling of solving problems together is really
great. And I also have to say sorry to my partners for my bad design of my
part to limit the function of our system.
<B82503081>
1. We can still improve the system through implementing the logic gate in the Control Unit, thus we can save the cost of logic gates.
2. If it’s possible, I suggest the wave-form between Control Unit and the Counter Unit be easier. (It mainly depends on the Counter Unit).
3. It is possible to make a twin-direction traffic light. It only requires 3 more inputs and 4 more outputs, so it can be implemented by the PALCE20 series PAL.
4. Because the wave-form of the Counter Unit varies with its design, so the Control Unit must match it. And because the Control Unit is a unit which can achieved by software work, so it’s more convenient to be altered than Control Unit. In the process of Experiment 1, the design of the Control Unit has changed for several times because of the change of Counter Unit. The wasting of time let me know the importance of communication between different engineers and a sure pre-design.
5. It’s very good to learn the concepts of state-machines. And I think if I can learn the PALASM more thoroughly, it would lessen the time of try-and-error. (Because bug is a troubling thing!) It let me know the importance of a whole(not fragment) concept of what a engineer will do.
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Selected Topics
[Deleted, because msot of them can be found in IC books]
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Appendix
1. The source code in PALASM of Control Unit
;PALASM Design Description
;---------------------------------- Declaration Segment ------------
TITLE Traffic Light Simulation Design
PATTERN Register
REVISION 1.3
AUTHOR Lan Chang of Group 6 in DCLAB
COMPANY NTUEE
DATE 10/08/96
CHIP _EXP1_6 PALCE16V8
;---------------------------------- PIN Declarations ---------------
PIN 1 CLK COMBINATORIAL ; INPUT
PIN 2 SW COMBINATORIAL ; INPUT
PIN 3 IG COMBINATORIAL ; INPUT
PIN 4 IY COMBINATORIAL ; INPUT
PIN 5 IR COMBINATORIAL ; INPUT
PIN 10 GND ; INPUT
PIN 11 /OE COMBINATORIAL ; INPUT
PIN 13 LG REGISTERED ; OUTPUT
PIN 14 LY REGISTERED ; OUTPUT
PIN 15 LR REGISTERED ; OUTPUT
PIN 17 OG REGISTERED ; OUTPUT
PIN 18 OY REGISTERED ; OUTPUT
PIN 19 OR REGISTERED ; OUTPUT
PIN 20 VCC ; INPUT
EQUATIONS
;----------------------------------- State Machine Segment -------
STATE
MOORE_MACHINE
START_UP:=POWER_UP->STATE_INI
;----------------------------------- State Assignment ------
STATE_INI=/LG*/LY*/LR*/OG*/OY*/OR
STATE_INI1=/LG*LY*/LR*/OG*/OY*/OR
STATE_G=LG*/LY*/LR*OG*/OY*OR
STATE_GY=/LG*LY*/LR*OG*OY*OR
STATE_Y=/LG*LY*/LR*OG*/OY*OR
STATE_YR=/LG*/LY*LR*OG*/OY*/OR
STATE_R=/LG*/LY*LR*OG*/OY*OR
STATE_RG=LG*/LY*/LR*/OG*/OY*OR
STATE_G1=LG*/LY*/LR*/OG*OY*/OR
STATE_G2=LG*/LY*/LR*OG*OY*/OR
STATE_Y1=/LG*LY*/LR*OG*/OY*/OR
;----------------------------------- State Transistion -------------
STATE_INI:=/SW->STATE_INI1+SW->STATE_G1
STATE_INI1:=/SW->STATE_INI+SW->STATE_G1
STATE_G1:=/SW->STATE_INI+->STATE_G2
STATE_G2:=/SW->STATE_INI+CY1->STATE_Y1+->STATE_G2
STATE_Y1:=/SW->STATE_INI+CR->STATE_YR+->STATE_Y1
STATE_G :=/SW->STATE_INI+CY->STATE_GY+->STATE_G
STATE_GY :=/SW->STATE_INI+->STATE_Y
STATE_Y :=/SW->STATE_INI+CR->STATE_YR+->STATE_Y
STATE_YR :=/SW->STATE_INI+->STATE_R
STATE_R :=/SW->STATE_INI+CG->STATE_RG+->STATE_R
STATE_RG :=/SW->STATE_INI+->STATE_G
CONDITIONS
CG=SW*IY*/IR
CY=SW*/IG*/IR
CR=SW*/IG*IY
CY1=SW*/IG
;----------------------------------- Simulation Segment ------------
SIMULATION
TRACE_ON CLK SW IG IY IR LG LY LR OG OY OR
SETF /CLK /SW
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
CLOCKF
SETF SW IG /IY /IR
CLOCKF
CLOCKF
CLOCKF
SETF SW /IG /IY /IR
CLOCKF
CLOCKF
SETF SW /IG IY
CLOCKF
CLOCKF
SETF SW IR
CLOCKF
CLOCKF
CLOCKF
SETF SW IY /IR
CLOCKF
CLOCKF
SETF SW IG
CLOCKF
CLOCKF
CLOCKF
SETF SW /IG /IR
CLOCKF
CLOCKF
SETF SW /IY
CLOCKF
CLOCKF
CLOCKF
SETF SW /IG IY
CLOCKF
CLOCKF
SETF SW IR
CLOCKF
CLOCKF
CLOCKF
SETF /SW
CLOCKF
CLOCKF
TRACE_OFF
;-------------------------------------------------------------------